1. Field of the Invention
The present invention relates to a semiconductor device having a reduced connection resistance value between wiring layers and a manufacturing method of the semiconductor device.
2. Description of the Related Art
As an example of a conventional manufacturing method of a semiconductor device, the following manufacturing method, shown in FIGS. 11A to 11E, has been known. As shown in FIG. 11A, a BPSG (boron phospho silicate glass) film 82 is formed on a silicon substrate 81. Subsequently, a contact hole 83 is formed in the BPSG film 82. Next, as shown in FIG. 11B, a titanium (Ti) film 84, a titanium nitride (TiN) film 85, an aluminum-silicon-copper (Al—Si—Cu) film 86, a Ti film 87 and a TiN film 88 are formed on and above the silicon substrate 81 by continuous spattering in a way they are embedded in the contact hole 83. Then, the above-described films 84 to 88 are then patterned by the use of a photolithography technique and an etching technique. Next, as shown in FIG. 11C, a plasma silicon nitride (SiN) film 89 and a TEOS film 90 are sequentially formed above the silicon substrate 81 by a plasma chemical vapor deposition (CVD) method. After an SOG film 91 is formed in the step portion, a TEOS film 92 is formed by a plasma CVD method. Next, as shown in FIG. 11D, a contact hall 93 is formed by a photolithography technique and an etching technique, having an upper portion on the Al—Si—Cu film 86 etched by 80 nm or more in depth. Next, as shown in FIG. 11E, a Ti film 94, an Al—Si—Cu film 95 and a TiN film 96 are formed above the silicon substrate 81 in a way they are embedded in the contact hole 93 and then they are patterned to form a wiring layer. (This technology is described for instance in Japanese Patent Application Publication No. Hei 9-219450, pages 3 to 5, and FIGS. 1 to 3.)
As another example of a conventional manufacturing method of a semiconductor device, the following manufacturing method, as shown in FIGS. 12A to 12F, has been known. As shown in FIG. 12A, an interlayer insulating film 102 made of silicon dioxide or the like is formed on the top surface of a silicon substrate 101. Then, as shown in FIG. 12B, an aluminum (Al) electrode pad 103 with a thickness of approximately 1.0 μm is formed on the interlayer insulating film 102. Next, as shown in FIG. 12C, a silicon nitride film 104 is formed on the interlayer insulating film 102 including the Al electrode pad 103 by a CVD method. Thereafter, as shown in FIG. 12D, an opening 105 is formed in the silicon nitride film 104 formed on the Al electrode pad 103. Next, as shown in FIG. 12E, a barrier metal film 106 is formed so as to coat the Al electrode pad 103 exposed at the opening 105. After that, as shown in FIG. 12F, a gold bump 107 is formed on the barrier metal film 106 by electrolytic plating. (This technology is described for instance in Japanese Patent Application Publication No. Hei 11-145171, pages 2 to 3, and FIG. 1.)
As described above, in the conventional manufacturing method of a semiconductor device, the contact hole 93 is formed in the plasma SiN film 89, the TEOS films 90, and 92 and so forth to connect the upper wiring layer and the lower wiring layer. At this time, the Al—Si—Cu film 86, the Ti film 87, and the TiN film 88 are etched as well, and thus, the Al—Si—Cu film 86 is exposed at the contact hole 93. In this manufacturing method, the Al—Si—Cu film 86 exposed at the contact hole 93 is oxidized, and therefore, an oxide film is formed on the exposed Al—Si—Cu film 86. As a result, the oxide film is formed in the current path between the lower and upper wiring layers, and this causes a problem that the connection resistance value between the lower and upper wiring layers is not likely to be reduced.
Further, in the conventional manufacturing method of a semiconductor, after the Al electrode pad 103 is formed on the interlayer insulating film 102, the silicon nitride film 104 serving as a passivation film is formed on the Al electrode pad 103. Then, the opening 105 is formed in the silicon nitride film 104 formed on the Al electrode pad 103, and the barrier metal film 106 is formed on the exposed Al electrode pad 103 by a sputtering method, for example. In this manufacturing method, in the step of forming the opening 105 in the silicon nitride film 104 and forming the barrier metal film 106 therein, the Al electrode pad 103 exposed at the opening 105 is oxidized to form an oxide film on the Al electrode pad 103. Thus, a current path on and above the Al electrode pad 103 is from the Al electrode pad 103 to the oxide film on the Al electrode pad 103, to the barrier metal film 106, and finally to the gold bump 107. As a result, there is a problem that the oxide film formed in the current path makes it difficult to reduce a resistance value on the Al electrode pad 103.